Joaquin Cabra Romero | Embedded Systems, Vision, and Hardware

What I do

Systems that have to survive contact with hardware.

My work sits where clean software abstractions meet physical systems: embedded communications, real-time classification, camera pipelines, FPGA logic, firmware, and the test tools that make each layer measurable.

Experience

Work that connects models, interfaces, and deployed systems.

Jan 2026 - Dec 2026

Embedded Software Engineer Co-op

CACI International, formerly Arka, Danbury, CT

Contributed across the full embedded software path for defense-oriented sensing platforms, from model architecture and real-time algorithms to communications, simulation, hardware testing, and customer-facing demos.

Created a novel convolutional neural network architecture for defense platforms.
Designed tracking and classification algorithms for real-time threat warning systems.
Built modular communication software across UDP, TCP, and serial networks for embedded targets.
Developed end-user graphical interfaces for customer demos and internal validation.
Ran hardware tests and wrote simulators that enabled full-path testing on a single machine.

Cabin workbench scene with defense platform reference models, snowboarding gear, and engineering monitors. — Embedded defense systems work: model-driven development, simulation, and field-oriented validation.

Jan 2024 - Present

Collegiate Tutor

Rochester Institute of Technology

Tutor computer science, math, and circuits for underrepresented and low-income students, helping students maintain a 100% passing rate and an average 1.5 letter grade improvement.

Jan 2024 - May 2024

Machine Learning Engineer Contractor

Data Annotation Tech, Remote

Evaluated annotator assessments of software engineering LLMs and helped improve the Achilles model on code generation, documentation, visualization, and analysis tasks.

Engineering stack

From low-level control to visual intelligence.

A practical mix of firmware, vision, machine learning deployment, hardware design, and desktop/web interfaces for demos, debugging, and validation.

01 Embedded communications

UDP, TCP, serial links, FDCAN firmware, SEGGER RTT, OpenOCD, Linux/bash, Docker, and real hardware bring-up.

02 Computer vision and ML

OpenCV, PyTorch, TensorFlow, ONNX Runtime C++ deployment, camera SDKs, GenICam, Basler Pylon, and LUCID Arena.

03 Digital design

VHDL, Verilog, ModelSim, Vivado, processor architecture, cache design, simulation, and board-level validation.

04 Interfaces and tools

React, TypeScript, JavaScript, Django, Spring Boot, Angular, WPF, C#, Python, C++, MySQL, and Jenkins.

Selected builds

Projects with a bench-side pulse.

Hardware, firmware, processor design, and web software, arranged like tools within reach.

Formula SAE

RIT Racing Team Electrical

Designed and tested regulation vehicle status lights, then wrote C firmware for FDCAN communication between boards used to validate suspension loads.

Altium C Firmware FDCAN

Processor design

32-bit MIPS Processor

Designed a pipelined RISC processor in HDL with instruction/data caches, hazard-aware control, and simulation-driven verification.

VHDL Verilog ModelSim

Full stack

Brogram

Built a full-stack social web app for programmers to discuss bugs, technical topics, and new technologies.

Django Python JavaScript

Visit project

Processor deep dive

Building a 32-bit MIPS processor from datapath to verification.

The MIPS project was not just an HDL exercise; it was a complete computer architecture build. I implemented a 32-bit reduced instruction set processor with a five-stage pipeline, separate 1 KB instruction and data caches, and control logic designed around the realities of hazards, memory access, and instruction flow.

I used VHDL, Verilog, and ModelSim to move from architecture diagrams into tested behavior, validating the datapath, pipeline registers, cache interactions, and timing assumptions through waveform-level simulation. The project strengthened the way I think about hardware/software boundaries: every instruction is both a software abstraction and a physical sequence of signals that has to arrive correctly.

32-bit RISC 5-stage pipeline 1 KB I-cache 1 KB D-cache ModelSim

Workbench scene with FPGA-style development boards, oscilloscope, laptop waveforms, and processor debugging tools. — Processor workbench: simulated waveforms, digital logic, and board-level thinking in one frame.

Outside the lab

Snowboards, fight gyms, and market structure.

I like systems with feedback: carving through snow, K-1 and Muay Thai training, race car electronics, and the discipline of options and futures trading. I also create educational content about contracts and trading tools at @skipacc.

Contact

Let's build where software has to touch the physical world.

I am especially interested in embedded systems, computer vision, robotics, digital hardware, motorsport electronics, and tools that make hardware development faster.

LinkedIn GitHub